The present invention relates generally to semiconductor device fabrication, and more particularly to shallow trench isolation (STI) structure fabrication process enhancements.
Isolation structures are used in semiconductor devices to electrically isolate different components of a semiconductor device. These isolation structures between the components reduce adverse noise effects that may cause performance degradation of the semiconductor device. Once the components are isolated from each other, certain electrical paths can be established between the components to obtain the desired electrical characteristics from the semiconductor device.
Conventional methods for fabricating an isolation structure for a semiconductor device typically employ a LOCal Oxidation of Silicon (LOCOS) process. In the LOCOS process, a field oxide layer is thermally grown using an oxidation mask to pattern the growth. However, a portion of the field oxide grows laterally, thereby producing tapering oxide wedge portions outside the desired growth pattern. These oxide wedge portions are referred to as a “bird's beak” due to the shape of the wedge portions. The bird's beak reduces the isolation area between the components of the semiconductor device and can deteriorate the electrical performance of the semiconductor device.
The shallow trench isolation (STI) process is replacing the conventional LOCOS process for the formation of an isolation structure as technology evolves to submicron geometries. The STI process has various advantages over the conventional LOCOS process. For example, the STI process allows for the planarization of the entire substrate and isolation structure. This results in better control of critical dimension (CD) when defining a gate stack of a transistor, for example. Better control of the CD when defining the gate stack results in better control of the CD in further processing steps, which occur after the gate stack is defined.
In a typical STI process, a buffer oxide of 10 to 20 nm is thermally grown on a wafer substrate. A nitride of approximately 200 nm is deposited and then patterned with lithography and etched down to silicon. An etch that is selective to silicon (etches mostly silicon) is then used to etch a trench into the silicon. A liner oxide is thermally grown to anneal out any damage to the silicon and passivate the silicon. Next, an oxide that is considerably thicker than the trench depth is deposited. The wafer is then subjected to a chemical-mechanical polishing that stops when it reaches the nitride. The nitride is then stripped, along with the buffer oxide underneath, thereby forming the STI structure.
For the above-described STI process scheme, the sharp corner where the trench sidewall meets the silicon substrate surface causes many problems with device performance, yield, and reliability. As an example, a parasitic transistor may be inadvertently formed at the corner that has a lower threshold voltage. As another example, a thinner gate oxide may be inadvertently formed at the corner, resulting in immediate device failure or reliability issues.
Other conventional STI process schemes have been devised to overcome the sharp corner effect by thermal oxidation processes, implantation of oxidation-accelerating ions and micro-structure transformation of silicon to round the corner where the trench sidewall meets the silicon substrate. Although these conventional rounding process schemes provide the corner rounding, they have inherent deficiencies. One deficiency of these conventional rounding process schemes is the stress-induced defect generation problem in today's reduced geometry device designs. A second potential deficiency is the damage of the STI sidewalls caused by the HDP oxide filling process of the oxide liner. Another deficiency is the divot-induced reverse narrow channel effect (RNCE) caused by parasitic corner transistors. This undesirable effect is due to the crowding of the electrical field at the STI edge.
Therefore, desirable in the art of semiconductor device fabrication are enhanced processes for shallow trench isolation (STI) structure fabrication that resolve the above deficiencies while increasing device performance, yield, and reliability.